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What is the boundary between a UVM driver and sequencer?DV ↗How should a SystemVerilog clocking/event question be sourced?DV ↗When should blocking and nonblocking assignment behavior be checked against IEEE 1800?DV ↗What is the UVM sequence-item handshake at a high level?DV ↗Why use the UVM factory instead of hard-wiring a component type?DV ↗What lifecycle concern do UVM objections address?DV ↗What question should functional coverage answer?DV ↗What makes an assertion property different from a test stimulus sequence?DV ↗